| Crate | Channels | Bars |
|---|---|---|
| b0wcal04 | 0-53 | 0-53 East |
| b0wcal05 | 54-107 | 54-107 East |
| b0wcal06 | 108-161 | 108-161 East |
| b0wcal07 | 162-215 | 162-215 East |
| b0wcal00 | 216-269 | 0-53 West |
| b0wcal01 | 270-323 | 54-107 West |
| b0wcal02 | 324-377 | 108-161 West |
| b0wcal03 | 378-431 | 162-215 West |
$ kinitIf the XBRD_DIAG register reads back the compliment of the value written then the Xilinx has been downloaded. If it reads out zero, or some value other than the compliment, then the Xilinx has probably not been downloaded since the crate was powered on. In this case, download the Xilinx by hand:$ rsh b0dap30 -l cdf_tof $ register b0wcal03 5 -set XBRD_DIAG 0xa5 [ 0] XBRD_DIAG <-- 0xa5 $ register b0wcal03 5 -get XBRD_DIAG [ 0] XBRD_DIAG = 0x5a
$ download b0wcal03 5After downloading the Xilinx from the on-board PROM, the download program checks the diagnostic register.
$ readadc b0wcal03 5 -get VCC5 [ 6.4] VCC5 = 2484 unipolar internal clock VCC5 voltage = 4.972 VHere is the list of ADC channels that can be monitored:
| ADC Name | Typical range | Description |
|---|---|---|
| VCC5 | +4.9...+5.1? | Analog +5 volts |
| VEE5 | -5.0...-5.2? | Analog -5.2 volts |
| VCC15 | +14.8...+15.2? | Analog +15 volts |
| VEE15 | -14.8...-15.2? | Analog -15 volts |
| VTT | -1.8...-2.2? | ECL termination voltage (-2 volts) |
| TEMP_T | 18...25 deg C? | Top temperature sensor (typically warmer than bottom sensor) |
| TEMP_B | 18...25 deg C? | Bottom temperature sensor (typically colder than top sensor) |
Which clock signal is monitored is controled by setting the CLOCK_MON register on the tomain board. For example, to check the common stop signal on the TOMAIN board in slot 5 of b0wcal03, you would check the channel map to learn that it's clock monitor is connected to channel 84 at the patch panel. Then, to enable the common stop on this output, you issue the command:
$ register b0wcal03 5 -set CLOCK_MON 0x04Here is the list of clock signals that can be monitored and the values to be written to the CLOCK_MON register:
| Signal | Value | Description |
|---|---|---|
| RESET | 0x01 | Reset signal received from LCF module |
| CAL | 0x02 | Calibration pulse from DDG, fanned out by CCFM/LCF module |
| STOP | 0x04 | Common stop, fanned out by CCFM/LCF module |
| OUT_CLOCK | 0x18 | ADMEM QIE output clock (only when ADMEM jumpered) |
| ADC_CLOCK | 0x28 | ADMEM ADC conversion clock (only when ADMEM jumpered) |
| QIE_CLOCK | 0x48 | ADMEM QIE cycle clock (only when ADMEM jumpered) |
| QIE_RESET | 0x88 | ADMEM QIE reset signal (only when ADMEM jumpered) |
$ register b0wcal03 5 -set CLOCK_MON 0
Monitoring of a given channel is enabled by setting the appropriate bit in the appropriate register.
To identify which TOMAIN board corresponds to which channel, which BNC connector at the patch panel corresponds to this TOMAIN board and what value nees to be written to the appropriate TOAD register, consult the channel map for the appropriate crate.
For example, to monitor the pulses on channel 87, you would consult the channel map for crate b0wcal05. Channel 87 is handled by the TOMAIN board in slot 8 of b0wcal05 which is connected to the BNC connector number 19. Channel 87 is the first channel on the third TOAD board and the command to turn on the monitoring is:
$ register b0wcal05 8 -set TOAD2 0x02The scope needs to be terminated into 50 ohms or else you will see a reflected pulse delayed by about 600 ns.
After you are finished monitoring pulses, please turn off the monitoring circuits:
$ register b0wcal05 8 -set TOAD2 0