Hello,

I have been refining my view of the diagnostics signals for the prupose
of specifying the layout of the diagnostics interface.  Look and tell 
me what you think.


FREE RUNNING SIGNAL:
1. SMCLK   the 132ns clock from the diagnostics interface.

SEQUENCED SIGNALS PROGRAMMED IN A FIFO
1. SMRST   the smqie reset signal.
2. SML1A   the level 1 accept signal.
3. SMDTR   the data transmit request.
4. SMWB0
5. SMWB1   the smqie write buffer numbers.
6. SMRB0   
7. SMRB1   the smqie read buffer numbers.
8. STIMULUS TRIGGER  the lvds stimulus trigger out.

PLD GENERATED PULSES (synchronized with the clock)
1. SMRST   the smqie reset signal (mode 2).
2. SML2R   the level 2 reject (stops dtr's).
3. SMSTRB  the load dac strobe.

SIMPLE REGISTERED SIGNALS
1. SMCALEN1  calibrate enable 1 (alias SML1A for bypass mode)
2. MODESEL0
3. MODESEL1  mode select bits (normal, current inj ena, source mon, bypass)
4. SMCALEN2  calibrate enable 2 (alias SML2R for bypass mode)
5. through 20. SMDATA[15:0]  dac data.
21. through 26. DIAGADR[5:0]  diagnostic address lines.


This considers SMXR Mode emulation and Bypass Diagnostics. 

Will this provide the intended functionality?


Craig