Level 2 ReCES Trigger
Specification for ReCES
Shower Maximum Bits Into the Level2 Interface Board for Run II
TrigMon Plots for ReCES
Description of Plots
Data Flow
; Details of data flow through the Frontend board to the ReCES board.
Board Schematics
; Diagrams of ReCES plus FPGAs to the ReCES board.
Last modified Dec 3, 2001
by byrum@anl.gov