SPY CONTROL BOARD Specifications

Franco Spinella, Luciano Ristori

March 21, 2001

 

INTRODUCTION

Spy Buffers: a powerful tool for SVT diagnostics

SVT is equipped with a very powerful built in diagnostic tool: the Spy Buffers. Data flowing through each input and output stream of every board are continuously copied into the Spy Buffers. There is one such buffer for each input and output stream of each SVT board. The purpose of these buffers is to spy all the data going by without causing any interference to the functioning of the SVT.

Spy Buffers act as built in logic state analyzers hooked continuously to internal SVT data streams and will help system monitoring and diagnosis. The contents of all buffers can be frozen at any time (e.g. on error detection) to take a snapshot of all data flowing through each SVT board. The concept is the same as when triggering a logic state analyzer.

Spy Buffers are implemented as RAM banks and each time a data word is popped from the input FIFO or pushed to the output stream of each board it is copied into the RAM and a pointer is incremented. The RAM is 23 bit wide and holds 21 bit data plus EP and EE. The pointer is the address where the next data will be copied. When the pointer overflows, it simply wraps around: incoming data will overwrite the buffer contents over and over in a circular fashion. At POWER ON the pointer is reset to zero. The Overflow Flag is set when the pointer wraps around the first time. This flag is used to validate all data in the buffer between the pointer position and the end of the buffer (flag set means all memory locations have been written at least once).

The buffers can be in one of two modes at any given time: SPY or FREEZE. When in SPY mode data are continuously copied into the RAM, when in FREEZE mode copying is suspended and the contents of all the buffers can be read through the VME interface without causing any interference to the data flow. The current value of the pointer and the overflow flag can also be read. Both the pointer and the overflow flag can be cleared through a VME write.

The main function of the Spy Control boards is to coordinate, at system level, the triggering of the Spy Buffers in response to the detection of an error condition.

SVT CONTROL LINES IN P2

4 lines in the P2 backplane are reserved for SVT use and are relevant to the Spy Control board. They are assigned as follows: Below is a short description of these signals.

SVT_ERROR

This line is active low and it is implemented as an open collector wired-OR. Pull-up resistor in located on the Spy Control board. It is used by individual SVT boards to signal the occurrence of error conditions to the Spy Control board sitting in the same crate. In each board the driving of the SVT_ERROR line is controlled by the Error Line Enable register: a number of different error types can be enabled to cause the SVT_ERROR line to go low (for additional details see the relevant sections in the documentation of each SVT board).

SVT_FREEZE

This line is active low and it is driven by the Spy Control board. It is used to freeze all Spy Buffers in all boards in a crate at the same time.

On receipt of the SVT_FREEZE signal (transition from high to low) the writing to the Spy Buffers must be immediately stopped in all SVT boards. The data and the value of the pointer to the circular buffer must be preserved (not overwritten) until the SVT_FREEZE signal is removed (transition from low to high). While SVT_FREEZE is low the data in the Spy Buffers and the Spy Buffer Pointer registers (including the Overflow Flag and the Spy Status) must be available for reading through VME. As soon as the SVT_FREEZE line goes high the writing to the Spy Buffers must resume starting from the current value of the pointer.

The Spy Status bit in the Spy Buffer Pointer register must be available for reading at any time and must yield the current status of the SVT_FREEZE  line. The values of the pointer and of the Overflow Flag are not guaranteed to be meaningful if read while SVT_FREEZE  is high. Any attempt to read the Spy Buffers while SVT_FREEZE  is high should result in a VME Bus Error.

SVT_INIT

This line is driven by the Spy Control board, it is active-low and it is used to initialize all SVT boards so that the whole system can be set in a well defined state in the shortest possible time. All boards that are in "Run" mode, on receipt of the SVT_INIT signal (transition from high to low), must immediately abort any data processing activity, reset all finite state machines, clear all FIFO's, discard any further input data and disable all outputs for the duration of the SVT_INIT signal (low level).  Each board that was in "Run" mode when SVT_INIT was asserted, must be ready to accept new input data as soon as the SVT_INIT signal is removed (low to high transition).

If a board is not in "Run" mode when SVT_INIT is asserted, the exact response is not specified. It is suggested that, in this case, the SVT_INIT signal is simply ignored.

What follows applies to all boards that are in "Run" mode when the SVT_INIT signal is asserted.

The SVT_INIT  signal must clear all error registers and global error flags.
The SVT_INIT  signal must NOT affect the content of spy buffers and pointers, error enable or disable, microsequencer programs, lookup table contents, AM contents etc. This is particularly important in order to ensure that we do not need to restore the contents of many registers in many boards as part of every Stop_Recover_Run cycle.
Care must be taken in order to ensure that if the SVT_INIT comes while the board is half way through one event, any error conditions encountered while processing the current event are not carried over to the End Event word of the following one.
The SVT_INIT signal will have a minimum duration of 200ns and some form of signal integration is recommended on each board in order to minimize the probability of spurious response to glitches.
All boards are expected to respond to SVT_INIT with a maximum delay of the order of a few hundred nanoseconds

SVT_LLOCK

This line is active low and it is implemented as an open collector wired-OR. Pull-up resistor in located on the Spy Control board. It is driven by the Hit Finder boards to signal the occurrence of a Lost-Lock error in a G-Link. It is received by the Spy Control board sitting in the same crate and transmitted to the Spy Master through the G_LLOCK line on the G_BUS cable daisy chain. The G_LLOCK signal is also sent from the Spy Master to the SVX front end through a dedicated cable.
 

SPY CONTROL REQUIREMENTS

General: errors and triggers

The main function of the Spy Control boards is to coordinate, at system level, the triggering of the Spy Buffers in response to the detection of an error condition. A typical situation would be an error detected by a single SVT board which must cause a global freeze: all the Spy Buffers in all SVT boards must be frozen immediately and their contents made available for inspection by diagnostic software. The normal way of operating the system would be to have any error detected in any crate to trigger all the Spy Buffers in all crates (Global trigger). For special purposes it is also possible to set up the system so that errors in one crate only trigger the Spy Buffers of that particular crate (Local trigger). The two modes of operation can be mixed to some extent so that, for example, one or more crates can be setup to respond to local (from same crate) and global triggers (from different crate) while others respond only to local triggers. The generation of a global trigger and the response to a global or local trigger can be enabled or disabled in each crate independently.

Programmable delay

The freezing of the Spy Buffers happens in response to a local or global trigger through a programmable delay. This gives the possibility of altering within certain limits the time relationship between the trigger and the data available in the Spy Buffers in a way very similar to the operation of the trigger of a logic state analyzer. Sometimes you are interested in investigating what happened after the trigger fired, at other times you want to see what happened before the trigger fired. By adjusting the programmable delay you can move the time window around the occurrence of the error.

SVT_INIT distribution

Another function of the Spy Control is the distribution of SVT_INIT to all crates so that the whole SVT system can be initialized and set in a well defined state with a single VME write to the appropriate location. It is also be possible to generate SVT_INIT to a single crate or a subset of crates by issuing one VME write per crate.

LEVEL1 counter

Spy Buffers are not directly affected by SVT_INIT in any way. When trying to understand data found in the Spy Buffers following a freeze it is important to know whether an SVT_INIT happened in a given time window. Following an SVT_INIT the data stream recorded by the Spy Buffers will probably show a "discontinuity" that will otherwise look like a malfunction. The LEVEL1 counter counts the number of Level1 triggers that occurred after the last SVT_INIT. When reading the Spy Buffers following a freeze the number in the LEVEL1 counter will tell us how many events we can safely "go back" before we bump into a discontinuity in the data stream caused by the occurrence of SVT_INIT.

The LEVEL1 counter is incremented by the LEVEL1 signal, halted by SVT_FREEZE and cleared by SVT_INIT. The counter is actually latched by SVT_FREEZE and SVT_INIT has no effect while SVT_FREEZE is asserted.
 

CDF_ERROR generation

Each Spy Control board has the capability of generating CDF_ERROR in response to SVT_ERROR and/or SVT_LLOCK. This function can be enabled/disabled locally in each crate or globally in the Master Spy Control. The typical reaction of the Spy Control system to a severe SVT error would be to trigger a global freeze to all the Spy Buffers and issue CDF_ERROR.

Spy Control Master/Slave

One Spy Control board sits in each SVT crate. All of them act as "Slaves" while one of them acts both as a "Slave" and as a "Master".

The tasks of a Spy Control Slave are:

  1. Detect errors on the local crate and convey this information to the Master
  2. Generate SVT_FREEZE on the local crate in response to an error in the local crate
  3. Generate SVT_FREEZE on the local crate in response to a command coming from the master
  4. Generate SVT_FREEZE on the local crate in response to a VME write to the appropriate location
  5. Generate SVT_INIT on the local crate in response to a command coming from the Master
  6. Generate SVT_INIT on the local crate in response to a VME write to the appropriate location
  7. Generate CDF_ERROR in response to errors in the local crate
  8. Count Level1 Accepts since the last SVT_INIT
The tasks of the Spy Control Master are:
  1. Generate a global freeze in response to errors detected by one or more Slaves
  2. Generate a global freeze in response to a VME write to the appropriate location
  3. Generate a global SVT_INIT in response to a HALT-RECOVER-RUN cycle
  4. Generate a global SVT_INIT in response to a VME write to the appropriate location
  5. Generate CDF_ERROR in response to errors detected by one or more Slaves
  6. Send SVT_LLOCK signal to SVX front-end
As a general rule all actions happening automatically in response to some particular event can be individually enabled/disabled by writing into appropriate VME registers (see below).

Information is exchanged between the Master and the Slaves through a cable daisy chain: the Global Bus (G_BUS).
Electrical and mechanical specs of the G_BUS are described below in the "Implementation" section.

IMPLEMENTATION

Mechanical specs

The Spy Control is implemented as one VME board (9U x 400 mm). Backplane connectors P1 and P2 are defined as per CDF standard. Two front panel connectors are used for the G_BUS daisy chain.

Master/Slave jumper option

The Master and the Slave sections of the Spy Control are both implemented on the same board. The Master section must be enabled in one and only one board in the system: we refer to this board as the "Master". The Master section of all the other boards will be disabled: this is done removing a number of jumpers in appropriate locations. We refer to these boards as the "Slaves".

G_BUS electrical and mechanical specs

The G_BUS is implemented as a cable daisy chain connecting all the Spy Control boards in the system (one per crate, including the Master).

The "beginning" of the chain is defined to be where the Master sits while the opposite side is defined to be the "end". The "downstream" direction is defined to be from "beginning" to "end" (Master to Slaves) while the "upstream" direction is defined to be from "end" to "beginning" (Slaves to Master).

Two front panel connectors are used for the BUS daisy chain. The two front panel connectors are mechanically identical but electrically different. The connector facing the Master side of the daisy chain (beginning of the chain) is labeled "UP";  the connector facing the opposite side (end of the chain) is labeled "DOWN". The correct way to build the daisy chain is to start with the Master and connect the "DOWN" connector of each board to the "UP" connector of the next one. The cable carrying G_LLOCK to the SVX SRC starts from the UP connector of the Master.

The cable carries four twisted pairs: they are used for the following signals:

Note that two signals (G_INIT and G_FREEZE) are flowing "downstream" and two signals (G_ERROR and G_LLOCK) are flowing "upstream".

Logic levels are LVDS and twisted pairs are 100 Ohm terminated. The drivers/receivers are implemented in such a way that if a cable is accidentally disconnected and the daisy chain is interrupted, all the modules upstream the interruption, including the Master, will get G_ERROR and G_LLOCK, and all the modules downstream will get G_FREEZE. G_INIT will stay false if not driven by the Master.

VME interface implementation

The implementation of the VME interface follows general CDF recommendations. Four address modifiers are implemented as follows: Any attempt to access a nonexistent address or to perform an illegal operation (e.g. writing to a read-only register) will result in a Bus Error.

Interrupt is not implemented.

Front Panel LED's

The following LED's are implemented on the front panel:

General:

Status of G_BUS output lines Status of SVT backplane lines CDF signals

VME REGISTERS

In the description of each register we only define the meaning of the relevant bit fields. All the remaining bits (undefined) are assumed to be ignored on write and zero filled on read. For each register we specify the internal address as a six digit hex number corresponding to the <23..0> bit field in the address bus. The <31..27> bit field is reserved for the geographical address of the board and the <26..24> bit field is required to be 0.
In the definition of the meaning of bits within a given register we always imply that a value of 1 corresponds to a logical TRUE and a value of 0 corresponds to a logical FALSE.

Different types of register are labeled as follows:

General Registers

0x000000 (R) : Jumper status

One jumper on the board enables the master section of the board and another jumper flags the slave at the end of the daisy chain (the master must sit at the beginning of the chain). The status of both jumpers can be read at this address.

0x000004 (R/W) : Lock register 1

General purpose R/W register. Can be used to implement a software lock access to SVT crates

0x000008 (R/W) : Lock register 2

General purpose R/W register. Can be used to implement a software lock access to SVT crates

0x00000C (R) : Firmware revision register

Contains the firmware revision formatted as an integer number. The firmware number is hardwired in the spycnl.spylogic verilog model

0x000010 (R/W) : Master/last mode

The spy control operating mode (master - lastinchain - normal) is configured at power on according to the master - last jumpers, but can be changed at run-time using this register. Pay attention that the MASTER - LAST leds reflect the jumpers status and not the operating mode.

0x100000 to 0x140000 (R) : ID PROM.

As per CDF specs. Data bits are <31..24>.

Slave Registers

0x000100 (R) : G_BUS Input Status

Status of the G_BUS input lines coming into front panel connectors.

0x000104 (R/W) : SVT_INIT Generation

This register is used to control SVT_INIT generation in the local crate (the one in which this board is sitting). Three options are available according to the <1..0> bit field status with the following codes:

0x000108 (W) : SVT_INIT Pulse

A write to this address generates a pulse on the SVT_INIT line on the local backplane. The duration of the pulse is approximately 1 microsecond. This can be used to quickly initialize all the boards in a crate.

This function will not work if the SVT_INIT line is already driven true by either G_INIT or by a code = 1 in the SVT_INIT Generation register. For this reason it is advisable to make sure that the SVT_INIT Generation register is cleared before attempting to use this function.

0x00010C (R) : Backplane Status

Status of the SVT lines on the local backplane.

0x000110 (R/W) : G_ERROR Generation

This register is used to control G_ERROR generation by the local crate (the one in which this board is sitting). Three options are available according to the <1..0> bit field status with the following codes: The G_ERROR line on the G_BUS performs the logical OR of all the G_ERROR drivers on the different Spy Control Slaves attached to the daisy chain. When the G_ERROR line becomes true at the Master end we usually want to know which board (or boards) is driving the line true. This information is obtained by polling bit <2> in this register.

Bit <2> is accessible only on read and displays the status of the G_ERROR driver on the board

Bit <2> is ignored on write.

0x000114 (R/W) : G_LLOCK Generation

This register is used to control G_LLOCK generation by the local crate (the one in which this board is sitting). Three options are available according to the <1..0> bit field status with the following codes: The G_LLOCK line on the G_BUS performs the logical OR of all the G_LLOCK drivers on the different Spy Control Slaves attached to the daisy chain. When the G_LLOCK line becomes true at the Master end we usually want to know which board (or boards) is driving the line true. This information is obtained by polling bit <2> in this register.

Bit <2> is accessible only on read and displays the status of the G_LLOCK driver on the board

Bit <2> is ignored on write.

0x000118 (R/W): SVT_FREEZE Generation

This register is used to control SVT_FREEZE generation in the local crate (the one in which the board is sitting).
Three signals (SVT_ERROR on backplane, SVT_LLOCK on backplane, G_FREEZE from Master) can be enabled to generate SVT_FREEZE through a bit mask. The mask is located in  the <3..1> bit field. Each bit enables the corresponding signal to set the FREEZE Flip-Flop. The flip-flop is set if the OR of all enabled signals is TRUE. The output of the flip-flop drives the SVT_FREEZE line on the backplane. Even if the generating signals are removed, the FREEZE Flip-Flop remains set until explicitly cleared by writing a 0 to bit <0>. Also note that the FREEZE Flip-Flop is not affected by SVT_INIT. The FREEZE Flip-Flop can be set by writing a 1 to bit <0>. To force SVT_FREEZE false, write 0 to all bits. To force SVT_FREEZE true, write 1 to bit <0>.
 

0x00011C (R/W) : SVT_FREEZE Delay

A delay can be programmed as a number of clock cycles to count between the setting of the FREEZE Flip-Flop and the appearance of SVT_FREEZE on the local backplane.

<15..0> = SVT_FREEZE Delay in steps of 1 microsec (from 0 to 65535)

This delay is effective also when SVT_FREEZE is forced true by writing a 1 into the SVT_FREEZE Generation register. You might want to set the delay to zero in this case.

This register is implemented as a down counter which is decremented by a 1 microsec internal clock while the FREEZE Flip-Flop is set. When the count reaches zero the SVT_ERROR line in the backplane is pulled true. The counter stops when it reaches zero effectively disabling the delay until a new count is preset by writing to the register through VME. In normal operation the FREEZE Flip-Flop must be cleared before the counter is re-initialized in order to prevent it from running quickly to zero while the flip-flop is still set.

0x000200 (R/W) : LEVEL1 Counter

Counts the number of L1 triggers occurred since the last SVT_INIT. It is incremented by the L1_ACCEPT signal from the Tracer, it is cleared by the SVT_INIT signal on the local backplane. Both incrementing by L1_ACCEPT and clearing by SVT_INIT are inhibited when SVT_FREEZE is true. The counter can be cleared by writing 0 even when SVT_FREEZE is true. The counter does not wrap around and stops when the count reaches the maximum value of 65535.

<15..0> : LEVEL1 Counter (0-65535)

0x000208 (R/W): CDF_ERROR Generation

This register is used to control CDF_ERROR generation in the local crate (the one in which this board is sitting).
Four signals (SVT_ERROR on backplane, SVT_LLOCK on backplane, G_ERROR, G_LLOCK) can be enabled to generate CDF_ERROR through a bit mask (G_ERROR and G_LLOCK can be enabled only if the board is configured as a Master). The mask is located in  the <4..1> bit field. Each bit enables the corresponding signal to set the CDF_ERROR Flip-Flop. The flip-flop is set if the OR of all enabled signals is true. The output of the flip-flop drives the CDF_ERROR line on the backplane. Even if the generating signals are removed, the CDF_ERROR Flip-Flop remains set until explicitly cleared by SVT_INIT or by writing a 0 to bit <0>. The CDF_ERROR Flip-Flop can be set by writing a 1 to bit <0>. To force CDF_ERROR to false, write 0 to all bits. To force CDF_ERROR to true, write 1 to bit <0>.

0x00020C (R) : CDF_RECOVER and CDF_RUN Status

Master Registers

These registers are accessible only if the board is configured as a Master. Any attempt to access these registers in a Slave board will result in a Bus Error (BERR).

0x000210 (R/W) : G_INIT Generation

This register is used to control G_INIT generation . Three options are available according to the <1..0> bit field status with the following codes: When response to CDF_RECOVER is enabled, G_INIT is set by CDF_RECOVER and cleared by CDF_RUN

Bit <2> is accessible only on read and displays the status of the G_INIT driver on the board

Bit <2> is ignored on write

0x000214 (W) : G_INIT Pulse

A write operation to this address will cause a G_INIT pulse to be generated on the G_BUS. Data is irrelevant. The duration of the pulse is about 1 microsecond.

This function will not work if the G_INIT line is driven true by either CDF_RECOVER or by a code = 1 in the G_INIT Generation register. For this reason it is advisable to make sure that the G_INIT Generation register is cleared before attempting to use this function.

0x000218 (R/W) : G_FREEZE Generation

This register is used to control G_FREEZE generation.
Two signals (G_ERROR and G_LLOCK) can be enabled to generate G_FREEZE through a bit mask. The mask is located in  the <2,1> bit field. Each bit enables the corresponding signal to set the G_FREEZE Flip-Flop. The flip-flop is set if the OR of all enabled signals is TRUE. The output of the flip-flop drives the G_FREEZE line on the G_BUS. Even if the generating signals are removed, the G_FREEZE Flip-Flop remains set until explicitly cleared by writing a 0 to bit <0>. Also note that the G_FREEZE Flip-Flop is not affected by SVT_INIT. The G_FREEZE Flip-Flop can be set by writing a 1 to bit <0>. To force G_FREEZE to false, write 0 to all bits. To force G_FREEZE to true, write 1 to bit <0>.

0x00021C (R/W): G_FREEZE Delay

A delay can be programmed as a number of clock cycles to count between the setting of the G_FREEZE Flip-Flop and the appearance of G_FREEZE on the G_BUS.

<15..0> = G_FREEZE Delay in steps of 1 microsec (from 0 to 65535)

This delay is effective also when G_FREEZE is forced true by writing a 1 into the G_FREEZE Generation register. You might want to set the delay to zero in this case.

This register is implemented as a down counter which is decremented by a 1 microsec internal clock while the G_FREEZE Flip-Flop is set. When the count reaches zero the G_FREEZE line on the G_BUS is pulled true. The counter stops when it reaches zero effectively disabling the delay until a new count is preset by writing to the register through VME. In normal operation the G_FREEZE Flip-Flop must be cleared before the counter is re-initialized in order to prevent it from running quickly to zero while the flip-flop is still set.