ALTERA Project for the Track Fitter

Introduction: In the Track Fitter board, five kinds of the ALTERA FPGA chips are used, and the total number of chips is 10. For the code development, the ALTERA MAX+PlusII V9.1 was used. The five kinds of chips are named "FEP", "FIT_BRAIN", "FIT", "OPP" and "VME_Interface". You can see more details below.
ALTERA Source Codes: Most of the codes are written in VHDL. Therefore, generally anyone who know the VHDL can understand the function of the codes. As exceptions, a few code are developed on the schematics editor of the MAX+PlusII. The source files are kept in /design/CDF_SVT/Track_Fitter/ALTERA/ directory in the UNIX machine of the EDG group in the University of Chicago.

FEP (ALTERA FLEX10K100ABC600-1) : "Front-End Processor"

The chip handles the data input part. The chip read the data from the INPUT_FIFO, and arraign them, and write the arraigned data into the downstream FIFO's for the next fit process.
FIT_BRAIN (ALTERA FLEX10K50VBC356-3) : "FIT chip control"

The chip controls six FIT chips for the timing and the setup of the memory lookup process.
FIT (ALTERA FLEX10K100ABC356-1) : "FIT Processor"

The chip perform the arithmetic calculation of the track fitting.
OPP (ALTERA FLEX10K100ABC600-1) : "OutPut Processor"

The chip get six fitting results from the FIT chip and pack them to ship them to the L2 interface board. The chip also perform the error handling, too.
VME_Interface (ALTERA MAX7000):

As the name, the chip is an interface between the VME bus and all other ALTERA chips. The chip decodes the VME signals.

The codes are compiled with VHDL 1993 (NOT. 1987) option.
The project file of each chip is kept as /design/CDF_SVT/Track_Fitter/ALTERA/XXX/XXX.tar.gz file. You can uncompress it by gzip and ftp it to a PC with binary transfer to see the project.
The project is developed with the machine, SHOP7 in the EDG group of University of Chicago, which is Window-NT machine with Pentium-II. The directory of the project is e:nakata/tf.