Tuesday, August 5, notes Present: John Anderson, Ed Barsotti, Aesook Byon-Wagner, Bob DeMaat, Bob Downing, Vince Pavlicek, Kerry Woodbury Kerry Woodbury, Vince Pavlicek and John Anderson met with the PCBCP to review the FIB (Fiber Interface Board), FIB Transition Module, and FIB Fanout module. The panel was provided with the following documentation: Completed PCBCP review checklists Pointers to the location of documentation available on computer. Fiber Interface Board -- Kerry Woodbury Kerry feels that the stiffener will block routing channels to J6 and doesn't want to add it. Perhaps a shorter version will work. This will be investigated. Relative to the possibility of mounting the subracks at a 45 degree angle, Kerry feels that this orientation makes it difficult to rotate the subrack in order to gain access to the transition cards. There would be no axis to rotate around that would allow gravity to hold the subrack in position. The subracks might also need to be oriented to allow the cards to be positioned with their component sides (versus solder sides) closest to the ground. The solder side cover thickness combined with the interface card(s) supports may be too large and cross over into the next board's space. Bob Downing would like Kerry to consider adding a second, horizontal stiffener. J5/J6 top shields are used for additional returns for single-ended signals. Bob Downing has learned that industry has experienced problems with the fingers on the shields of the 2-mm hard metric connectors bending. Amp has implemented a fix but ERNI has yet to do the same. Test & repair needs: The FIB requires an open-side subrack, a DEM (Detector Emulation Module) and an FIB Fanout under the control of an IBM compatible PC. Additionally, an interface board set, such as those made by Bit-3 Inc., will be necessary. The FIB requires -5.2 volts on the P0 connector utilizing the Vw, Vx, and Vy buses. It draws 7 amps at 5 volts which is fused at 10 amps. It draws 4.6 amps at -5.2 volts which is fused at 7 amps. Transorbs are used on the module. The common-mode issue of grounding between the subrack and power supplies needs to be addressed by the Grounding & Shielding committee. I/O on the front panel is implemented with four optical connectors. The J5/J6 connectors utilize both TTL and ECL signals. Clock sources: there is currently one for the Fanout but the production FIB will also have a crystal for the G-Links. The FIB prototype currently has geographical address dip switches to allow it to operate in older subracks. Ed recommends that these be removed for the next version of the board. The ECL power plane layer of the circuit board is divided into a -5.2V area and a -2V area. This layer is sandwiched between two other power planes so it is not an impedance-control plane. To achieve improved air flow, resistor sips that are mounted horizontally will be moved on the next layout to a vertical orientation. The package style for the 500-ohm pulldown resistors used for the G-Link interface will be changed from a common-pin style to a package the consists of resistors that do not share a common pin. "Air resistor" filler boards need to be ordered. Vince Pavlicek has gotten some from Dawn, Inc. Bob Downing thinks that the FASTBUS version MIGHT work in this application. The technology for the VMEbus interface transceivers may be changed to a version manufactured by either IDT or Harris for improved (slower) edge speed. The module ID is different from VME64 and CDF2388. The FIB VMEbus interface supports A32/D32 transactions. It does not support block transfers. Address modifier code 0A is the only one supported at this time. 09 and 0B will be added. The software developed by Jim Pangburn includes a feature that analyzes upcoming VME transfers and, where it might improve efficiency, automatically combines single transfers into block transfers. However, some modules (the FIB included) do not support block transfers and, for diagnostic purposes, it would sometimes be good to be able to communicate with modules that do support block transfers with single transfers. Bob DeMaat will talk to Jim Pangburn about how to disable this feature. The ESD traces are covered with solder mask on the current version of the FIB prototype board. This will be changed in the next version. Operating modes: The FIB has a Run mode as well as several diagnostic modes that are used to test the FIB, the Port Cards, and the SVX IC's. A shortcoming of the cabling installation is that, due to a lack of routing channels, there is not enough signal wires available to provide the status information necessary to determine exactly where a stuck bit would be located in the loop from the FIB to the SVX IC's and back to the FIB. Initialization, calibration, and diagnostic software is being developed by Colin Gay and his colleagues. The current rating for the fuses will be added to the silkscreen layer. For diagnostic purposes, all bits that can be written to the FIB can also be read. ============================================= FIB Transition Module -- Vince Pavlicek There are two versions: Copper and Optical. Due to there being a large number of connectors on the front of the board, there is no front panel on the copper version. The copper version will only be needed if the DOIM fails. However, Aesook pointed out that there is not room for copper cables in the cable channels so the DOIM MUST work and the optical version will be used (for CDF). Connections are made on J0 and J5/J6 with the shell on J2 used for alignment purposes. The nuts used to mount the voltage regulator and the connectors are too thick and will need to be changed for the production version. The optical version is expected to dissipate 18 to 20 watts (~4 amps @ 5 volts). Power will be provided by pins on connector J0. Good cooling practice will be required in the transition card region. Cooling the DOIM may be a challenge. The optical board will have a stiffener and a front panel. The Taiwanese don't want a heat sink on the DOIM but Vince and Ed feel that a heat sink will be necessary. The fibers will need to be secured at the DOIM on the transition card and perhaps at other locations on the card as well. The current version of the FIB Transition Module has a twin-connector assembly that sends LVDS signals to two Port Cards. This assembly integrates two 26-pin connectors in the footprint of one by effectively mounting one atop the other. However, the height that the connector pair rises above the board is greater than allowed by the VIPA spec and would cause the connector to scrape against the bottom of a board located in an adjascent slot. A different solution to this connector issue will have to be implemented. One approach could be to use two separate 26-pin connectors, one of which is mounted at the edge of the card while the other is behind the first, toward the center of the card. To connect a cable to this second connector would require that the transition card be removed from the slot. Another approach would be to change connectors altogether. The value of the fuse will be included on the silkscreen of the next version of the card. An LED indicating that the card is powered will be included on the front panel. No clocks are input to either version although the Optical version has its own clock. In order to test the FIB Transition Module an FIB with a loop-back cable is required. To do high-speed tests, a Data Emulator Module (DEM) driving fiber data and a second FIB module is required. The software has not yet been written. ============================================== FIB Fanout Module -- John Anderson The first prototype did not get milled at the fab house. The next version will be milled to the proper thicknessd. Revision B of the board will have stiffeners. There are no components mounted on the solder side. The solder-side cover will cover jumper wires on the prototype. The shield on the Amp connector on the front panel is connected to the front panel as well as the shield on the cable. This approach will have to be evaluated by the Grounding & Shielding Committee since it is different from what the committee recommends. The DB-25 programming connector is mounted to the front panel and may or may not be grounded. John will check. The Fanout Module uses -5.2 volts (bused on Vw, Vx, and Vy) and +5 volts. -5.2V draws 2 amps and is fused at 5A. +5V draws 3 amps and is fused at 5A. Transorbs are used. A mounting hole for a center support for the front panel is included on the circuit board but it is probably not necessary since several connectors mechanically mount to both the circuit board and front panel. The current version includes Geographical Address selector switches that are no longer needed with the card residing in a VIPA subrack. These switches will be removed from the next version of the card. Checkout and repair requires a GSTM and daughter card to implement the FIB Fanout status connector. The daughter card requires modifications. A FIB is necessary as well as an open-side subrack equipped with a VRB/FIB J3 backplane. An IBM compatible PC is also required. Diagnostic software. Run mode: Software diagnostic code developed by Colin Gay. Initialize mode: No software required to initialize. The Fanout module has a test FIFO that can be downloaded with data. Front panel connectors carry optical and LVDS signals. The 235-pin J5/J6 connector carries ECL and TTL signals. Some of the trace lengths for the VMEbus interface will be reduced in the next version of the card. The Fanout module has the option of using an internal 53 MHz clock or a clock supplied by the SRC module. The printed circuit board is implemented with two voltage planes and a common return plane. The SVX module ID appears at the lowest memory location. The Fanout module responds to address modifier code 0xA only though this is PLD programmable. It transfers single words only and is an A32/D32 slave. Block transfers are not supported. ====================================== If you find inaccuracies (or omissions) you would like to have corrected, please send comments to Bob DeMaat. demaat@fnal.gov fnald::demaat