From:	FNALD::KPITTS       "Kevin Pitts" 14-NOV-1998 13:44:37.22
Subj:	calibration pulse delays


Here are my estimates for the variations in the arrival
time of the calibration strobe at the various ASDQ 
daughterboards.

SL E/W  ucoax   TDC slots     min delay   max delay
-- ---  -----   ---------     ---------   ---------  
1   E    14'      4-5         0.0 by def     0.4ns
2   W    14'      4-5            0.0ns       0.4
3   W    13'6"    6-8           -0.8         0.0                
4   E    13'6"    5-8           -1.1         0.0
5   E    13'      8-12           0.0         1.5
6   W    13'      8-12           0.0         1.5
7   W    12'6"    12-17          0.7         2.6
8   E    12'      12-17          0.0         1.8

The "TDC slots" column lists the lowest and highest slots 
that any TDC from a given SL resides in.

The minimum and maximum delay are calculated relative
to a SL1 board in slot 4.  

The delay is calculated as:
   delay = (slot - 4)*0.37ns/slot - (1.5ns/foot)*(length-14')
                 ^slot-to-slot         ^cable length

I have assumed that the delay across the backplane is
7ns from end to end (slots 2->21), which translates to
0.37ns/slot, assuming it's linear across the backplane.

I have assumed 1.5ns/foot for the ucoax.

So the range of delays is -1.1ns to +2.6ns.  Given that
the delay through the ASDQ is about 12ns, it looks like
it is fine to keep all of the flat cable lengths the same.

This calculation assumes the TRACER to be in slot 2.
If we put it in the middle, the range gets worse, because
as it is now, the backplane delay is somewhat compensated
by the shorter ucoax lengths for the outer SLs.

Unless anybody has a problem with this, I will update the
baseline calibration plan to include all flat cables the
same length.  Also, I will update our readout mapping to
have the TRACER in slot 2.