SPECIFICATIONS FOR THE CDF QIE
                      March 20, 1996 - C. Nelson


0. GENERAL DISCUSSION
---------------------
     These specifications for the CDF QIE are based on the assumption
     that the general architecture will be that of the QIE5, and that,
     consequently, no discussion or specification of its general theory
     of operation is necessary. Many details, such as power supply levels,
     which clock edges initiate which actions, etc., are left to the IC
     designer to specify. Also, some of the items below are not so much
     specifications, but rather statements of understanding about QIE
     characteristics.

     The term "response range" refers to one of the eight current ranges
     for one of the four sets of integration capacitors. Thus there are
     32 response ranges.


1. ANALOG INPUT
---------------
     Full scale input charge:    -1300 pC.

     Max. instanteous current:   -50 mA.

     Quiescent voltage:          +1 volt, nominal.

     Small signal impedance:     150 ohms, or less.

     Maximum voltage swing:      -2.7 volts, from quiescent level.


2. ANALOG OUTPUT
----------------
     Mode:                       Differential.

     Differential output range:  0 to 1 volt, nominal.

     Common mode:                Between +3 volts and +9 volts is acceptable.

     Output settling:            Driving a 10 pF load (additional to the QIE
                                 chip and its case), the output must settle
                                 sufficiently within 100 nsec after the
                                 corresponding clock edge that the other
                                 specifications are met, particularly linearlty
                                 and stability.

     Output droop rate:          Less than 1 mv per nsec, after 100 nsec of
                                 settling time.
                              .
     Equivalent noise charge:    Less than 0.2% of input charge or 10 fC,
                                 whichever is greater.


3. DIGITAL I/O
--------------
     Inputs:                     CLOCK and RESET.

     Input levels:               Single-ended TTL, internally buffered.

     CLOCK frequency:            7.6 MHz  ( 1/132 nanoseconds ).

     RESET operation:            Must be completed within 50 nanoseconds after
                                 assertion.
     
     Outputs:                    3 current range bits and 2 capacitor ID bits.

     Output levels:              Single-ended TTL.

     Output settling:            With a 10 pF load (additional to the QIE
                                 chip and its case), the data must be valid
                                 within 50 nsec after the corresponding clock 
                                 edge.



4. LINEARITY AND STABILITY
--------------------------
     Linearity:                  The linearity of each of the 32 response ranges
                                 must be such that a least-squares fit of any
                                 range, with 5 equally spaced measurement
                                 points, will allow the input charge to be
                                 reconstructed to within 0.2% of itself or
                                 10fC, whichever is greater. The input charge
                                 is to be reconstructed using the slope and
                                 offset obtained for the particular response
                                 range under test.

     Temperature stability:      The reconstructed input charge must vary by 
                                 less than 0.2% per degree C., or 10 fC per
                                 degree C., whichever is greater.


     Time stability:             The reconstructed input charge must vary by 
                                 less than the greater of either 0.2%  or 10 fC
                                 in any four hour period, when temperature and
                                 power supply levels are held constant.

    
     Power supply dependence:    The reconstructed input charge must vary by
                                 less than 0.2% or 10fC, whichever is greater,
                                 for a 1% or 50mv change in any supply voltage,
                                 whichever is greater.



5. POWER SUPPLIES
-----------------
     Voltages:                   Positive supply voltages and ground. Exact
                                 values to be determined by the IC designer.



6. OPERATING ENVIRONMENT
------------------------
     Temperature range:          20 degrees C. to 55 degrees C.