TDC Full Crate Test

The TDC Full Crate Test refers to a test stand operation at CDF testing the University of Michigan TDC96 boards. These are 96 channel VME boards, in the 9Ux400mm format, built around the JMC96 TDC ASIC.

Test Goals:

• Evaluate performance of TDCs with up to 18 TDCs operating in the same crate simultaneously.
• Verify power supply performance during operation of multiple TDCs
• Connect to VRB to test DAQ readout path
• List of planned tests

Talks on Full Crate Test Results

• Status of TDC Full Crate Test: Overview of test plans and power supply scope pictures. March 3 1999, DAQ Meeting, by Peter Wilson.PowerPoint or Postscript
• Status of TDC Full Crate Test: Analysis of calibration data. March 3 1999, DAQ Meeting, by Bill Orejudos. Postscript
• Status of TDC Full Crate Test: More Analysis of calibration data. March 22 1999, LBL Group Meeting, by Bill Orejudos. Postscript

Test Result Summaries

• Bunch counter counting errors which have been traced to CDF_CLK termination problems (Oct-Nov 1998).