Agenda for 4th Annual Electronics/DAQ upgrade Workshop ====================================================== Time: Jan 27-29, 1999 Place: UCLA Information on travel, lodging, direction, & registration at http://www-collider.physics.ucla.edu/cdfdaq/workshop.html ************* * DAY 1 * ************* 8:30 - 9:00 Workshop Registration (& continental breakfast) 9:00 - 9:10 Welcome Jay Hauser 9:10 - 9:30 Run2 Schedule Bob Kephart Session I Remaining issues for Production & Status of documentations ------------------------------------------------------------------------- Session organizers: Jay Chapman & Bill Foster 9:30 - 10:00 SVX DAQ & VRB Colin Gay 10:00 - 10:30 Tracking FE & Trg Mike Kelly/Kevin Pitts (COT & muon: TDC, XFT, XTRP, L1 muon) 10:30 - 10:45 Coffee Break 10:45 - 11:15 Calorimeter FE & Trg Mike Lindgren (ADMEM, Hadron ASD, SMX, L1cal, L2cal) 11:15 - 11:45 Lv1 & Lv2 Decision Crates and SVT Luciano Ristori 11:45 - 12:15 TSI, Clock & TRACER Michael Schmidt 12:15 - 1:15 Lunch 1:15 - 1:45 Level3 trigger, Event Builder Steve Tether Consumer Server, & Data Logger 1:45 - 2:00 Discussion Cover following questions: (1) Any unresolved performance issues and remaining tests to do. (2) Any unresolved system protocol or system integration issues? (3) Any unresolved hardware & software infrastructure related questions? (4) Current production schedules (for major pieces) (5) Do you have any special reset or recover conditions (ie. not meet the specs for CDF standard reset/recover) which were observed with your prototype modules or systems? (6) List of design and user documents and the location of documents (also indicate a category of existing, in preparation, or need to be written) (7) List of online software and its location (indicate category - existing, in preparation, need to be written) Please do NOT go over (Assume that everyone knows what your system does) (1) Lengthy system overview (1 or 2 slides ok but no more than 2) (2) Any detailed design description (3) Any history of tests which have been done and the problems which already have been solved Session II Trigger Supervisor Session - Part I ------------------------------------------------------------------------- Session organizers: Michael Schmidt & Steve Vejcik 2:00 - 2:30 Overview of TS Michael Schmidt 2:30 - 2:50 Special arrangement for modest operations and test facilities Andrew Martin 2:50 - 3:30 Discussion on how to implement P Wilson & E James TS emulation for various integration test & commissioning 3:30 - 4:00 Error handling/reporting, Jim Patrick Sys_init, Sys_reset from Run_Control point of view 4:00 - 4:15 Coffee Break Session III Infrastructure & Commissioning ------------------------------------------------------------------------- 4:15 - 5:15 Updates on Electronics Infrastructure Peter Wilson - crate, power supply, CPU - Survey of cases/conditions of various module/crate reset/reboot - Backplane signal properties - Guideline for spare parts - B0 maintenance support issues 5:15 - 6:00 B0 Commissioning schedule Hans Jensen & discussion for Day3 sessions 6:00 - 8:00 Break for Dinner 8:00 - 10:00 * If needed, Small meeting rooms will be available for group meetings in parallel ************* * DAY 2 * ************* 8:30 - 9:00 Continental breakfast Session IV Trigger Supervisor Session - Part II ------------------------------------------------------------------------- Session organizers: Michael Schmidt & Jim Patrick 9:00 - 10:00 TS session continue (part 2) Schmidt/Patrick More discussions and answers to the questions from the session in Day 1 10:00 - 10:15 Coffee Break Session V Trigger Algorithms ------------------------------------------------------------------------- Session organizers: Dave Saltzberg & Jay Chapman 10:15 - 10:25 Access Methods to the Database Rick Vidal 10:25 - 10:35 Lv1 Decision (FRED+PreFRED) Greg Feild 10:35 - 10:45 Lv1 Calorimeter (DIRAC+CRATESUM) Ray Culbertson 10:45 - 11:00 Muon system Eric James 11:00 - 11:10 Lv2 Calorimeter (DCAS,CLIQUE...) Monica Tecchio 11:10 - 11:30 XFT (Finder, Linker, XTC) Brian Winer 11:30 - 11:40 XTRP Nathan Eddy 11:40 - 11:55 L2 Interface boards Jane Nachtman (XCES,Track,Muon,L1) 11:55 - 12:10 L2 processor Stephen Miller 12:10 - 1:10 Lunch break 1:10 - 1:30 SVT Tsuyoshi Nakaya 1:30 - 2:00 Level 3 trigger Kevin McFarland Cover following questions: (1) Describe the algorithm (2) What data do you need FROM the database? (3) What data do you need to put INTO the database? (4) What Xilinx programs will you be downloading? How large are these programs? How often will they change? (5) What software exists for simulating the algorithm? Where is it? (6) What software exists for debugging the hardware? Where is it? (7) What software tools do not exist yet, but must exist? ** NOTE ** 10:30 - 2:00 *If needed Small meeting rooms will be available for frontend electronics group meetings in parallel Session VI System integration test ------------------------------------------------------------------------- Session organizers: M Lindgren, M Campbell & M Schmidt 2:00 - 2:30 calorimeter FE+trigger (Lv1 & Lv2) Monica Tecchio 2:30 - 2:55 muon FE+trigger (include hadron TDC) Eric James 2:55 - 3:25 COT FE+XFT+XTRP Jonathan Lewis 3:25 - 3:55 Lv1 trg (cal+XFT+XTRP+muon+preFRED+FRED) Greg Feild 3:55 - 4:10 Coffee Break 4:10 - 4:30 SVX FE+SVT Ray Culbertson 4:30 - 5:00 Lv2 trg (interfaces+SVT+processor) Stephen Miller 5:00 - 5:30 Lv3 trg (EVB+LV3+CS+DL) Paus/McFarland 5:30 - 6:00 Trigger system Integration (Lv1, Lv2 & Lv3) Peter/Patrick Go over following issues: (1) Briefly go over integration test which has been done already (2~3 slides) (2) How the integration test will be done (would be good if can be broken into a few number of steps - somewhere around 5~10 steps) then for each step, (3) location (where the test will be done), schedule, manpower (4) Detailed list of tests (ie goals) to be done (5) List of hardware infrastructure needed (6) List of software needed and how you plan to integrate them (unless they are already integrable such as in CDFVME package) 6:00 - 8:00 * If needed, Small meeting rooms will be available for group meetings in parallel 8:00 - 10:00 Break for Dinner ************* * DAY 3 * ************* 8:30 - 9:00 Continental breakfast Session VII B0 hardware & software installation & Commissioning ------------------------------------------------------------------------- Session organizers: Hans Jensen, Peter Wilson & Jim Patrick 9:00 - 3:00 B0 hardware & software installation plans for Feb-Oct '99 9:00 - 9:25 TSI Michael Schmidt 9:25 - 9:40 Clock Kaori Maeshima 9:40 - 10:00 CLC Andrei Nomerotski 10:00 - 10:20 SVX Colin Gay 10:20 - 10:35 Coffee Break 10:35 - 11:00 Calorimeter FE (ADMEM+SMX+HadTDC) Mike Lindgren 11:00 - 11:15 Lv1 & Lv2 Cal Trg Monica Tecchio 11:15 - 11:35 TDC Myron Campbell 11:35 - 11:55 XFT Richard Hughes 11:55 - 12:10 XTRP Lee Holloway 12:10 - 12:30 Lv1 muon trg Jay Chapman 12:30 - 1:30 Lunch 1:30 - 1:50 SVT Henry Frisch 1:50 - 2:05 Lv1 Decision Greg Feild 2:05 - 2:20 Lv2 Decision Karen Byrum 2:20 - 2:35 VRB/EVB/SCPU Steve Thether 2:35 - 2:50 Lv3 Trigger Chris Paus Cover following questions: (1) Hardware installation Schedule (when and how many of first batch hardware will be delivered to B0, when 50%, 100%?) (2) Manpower (who will show up at B0 when) (3) List of test to be done on each stage (first batch, 50%, 100%) (4) What else needed to be working when your system shows up (infrastructure, neighboring system, software etc) 2:50 - 3:05 Coffee Break 3:05 - 5:30 Discussion for Scenario of Hans Jensen/Jim Patrick - Commissioning Run (beam-off, beam-on) - Debugging Run - Calibration Run - Normal Data taking Run Final Session Bill Foster ------------- 5:30 - 6:00 Summary & Top 10 list