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A pA (# @ R e s o u r c D , o @ @w[A (# T@ R e s o u r c D , o @@ UA (# H R e s o u r c @ , D , o A @w{A (# Y@ R e s o u r c @ , D , o L@ pdA @ R e s o u r c D , o L@ pdA @ R e s o u r c D , o @ @w[A @ R e s o u r c D , o @ @w[A \@ R e s o u r c D , o @ @wKA ]@ R e s o u r c D , o @ @wKA ^@ R e s o u r c @ , 4 $ ` D , o 4 $ ` D , o A `A : @ R e s o u r c D , ` L@ *A : @ r \r D , @ `fA : @ u r c 0 @R D , o A `A : @ R e s o u r c @ , D , o L@ @w[A @ R e s o u r c D , o L@ @w[A @ R e s o u r c D , o @ ORA @ R e s o u r c D , o @ ORA \@ R e s o u r c D , o @ OBA ]@ R e s o u r c D , o @ OBA ^@ R e s o u r c D , o @ R e s o u r c D , o @ R e s o u r c D , o jA 8A 0u @ R e s o u r c D , L@ *A 0u @ r @ V @ @[r +@ D , @@ ObA 0u @ H Q D , o @ `vA 0u I R e s o u r c @ , @ , 0 $ * d h N b * @ @ X * @ , 4 $ ` D , o 4 $ ` D , o A OA . R e s o u r c 4 $ ` D , o A OA . R e s o u r c 4 $ ` D , o @ OrA . 8@ R e s o u r c 4 $ ` D , o @ ObA . 9@ R e s o u r c 4 $ ` D , o A OA . @ R e s o u r c 4 $ ` @ , D , o 4 $ u J A l D , o 4 $ D , o @ ObA p @ R e s o u r c D , @ ORA p @
Q D , o A OA p @ R e s o u r c @ , D , o @ ObA . 5@ R e s o u r c D , o A OA . 6@ R e s o u r c D , o @ ObA . 7@ R e s o u r c D , @ ObA p @ p e r a t i o n D , L
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A 0" D , o A OrA p :@ R e s o u r c D ,
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A 0" D , o @ ObA p +@ R e s o u r c D , o @ ORA p ,@ R e s o u r c D , o A OrA p -@ R e s o u r c D , o D , o D , p @ OrA . @ S a v e C o p y A s D , ` A pA . .@ ` ` ` ` D , @ ObA . @ P eD , D , l A `A 0u @ t e C h e c k D o n D , A `A 0u 0@ 0b 0b D , 0 @ `vA 0u @ '` P D , o @ `vA 0u s@ R e s o u r c D , @ `A 0u o D , #A `A 0u @ p e r a t i o n D , o @ `A 0u L@ R e s o u r c D , o A `A 0u M@ R e s o u r c D , o @ `vA 0u ^@ R e s o u r c @ , 0 $ * d h N b * @ @ X * @ , 0 $ 0 * d h NcM bcM * @ @ XcM * D , o @ ObA p l@ R e s o u r c D , o @@ L=A p m@ R e s o u r c D , o @ ObA p n@ R e s o u r c @ , a D , o 4 $ N! @ , 4 $ N! @ , @ , 4 $ N! D , @ @wkA (# \@ w @w D , G A @w{A (# %@ k PQ D , o @ @wkA (# \@ R e s o u r c D , o @ @wkA (# a@ R e s o u r c D , @ ObA p ]@ @t D , @ A OrA p &@ ' ' Q D , o A OrA p `@ R e s o u r c D , o ^@ R e s o u r c 4 $ N! D , o _@ R e s o u r c 4 $ N! D , o A @w{A (# d@ R e s o u r c D , o @ @wkA (# e@ R e s o u r c D , 0 @ ObA p ^@ w t C h w D , A OrA p '@ P D , o A OrA p b@ R e s o u r c D , o 4 $ N! D , o 4 $ N! D , A OA . J@ e 0e D , @ OrA . U@ @t @t D , @ OrA . `@ y y D , @ ObA . )@ '` P @ , D , o @ @w[A (# R e s o u r c D , A @w{A (# *@ ` O D , o A @w{A (# f@ R e s o u r c @ , 4 $ N! D , o 4 $ N! @ , D , o @ , 4 $ N! D , o 4 $ N! D , A @w{A (# w@ y |y 4 $ N! D , @ @wkA (# @ Pv 4 $ N! l 0 @
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A @w{A (# @ y wy D , @ @wkA (# @ Ў `pЎ D , @ @wkA (# 9@ ` @M D , @ ObA p @ Ў D , @ ORA p :@ D , o A OrA p z@ R e s o u r c @ , D , o D , o @ ObA p R e s o u r c D , o @ ObA p R e s o u r c D , o @ ORA p R e s o u r c D , n @ ObA p @ @ D , 0
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e! K! gA gA 'O ? @ w w 4'O @~ 0 4''3 'l ? w w 'k' ptA 4%0A 4%0A L L @_Q ' ' # ' <A <A *A *A ' 00-0000-0000-000000000000}#0.0#0## MSForms> M S F o r m s 0 *\G{86D658C6-3856-4A9A-AD87-F1F4FD8DB89E}#2.0#0#C:\DOCUME~1\brenna\LOCALS~1\Temp\VBE\MSForms.exd#Microsoft Forms 2.0 Object Library .E
.`M L @S! \ @+ @+ k 'Z # ' ưA ưA plgA plgA ' + " Then
totalUS = totalUS + a.cost
End If
Next a
t.Cost1 = totalUS
Call SummaryCosts(t, 1)
End If
Next t
End Sub
Sub USEstim()
For Each t In ActiveProject.Tasks
t.Cost2 = 0
If t.Summary = n e 'N $ $ K ' '
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! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
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! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
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! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D 9 G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~ 1 . @ R u n 2 b S i l i c o n D e t e c t o r S c h e d u l e 1 ļB 1 . 1 . R u n 2 b S i l i c o n P r o j e c t 1 >I 9 Y!A A A 6A `sA l̘A 1 . 1 . 1 D A Q 1 : 1 1 A 4_A 6A `+A ڋA 1 . 1 . 1 . 1 S V X 4 C h i p s 1 % 2 7 @
A \^A gA @ vA nZA2 {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
{\colortbl ;\red0\green0\blue0;}
\viewkind4\uc1\pard\cf1\f0\fs16 Runs:\par
1. Prototype (Hybrid #1) \par
2. Contingency (Hybrid #2)\par
3. Production (Preproduction and Production hybrids)\par
\cf0\par
\par
}
1 . 1 . 1 . 1 . 1 P 1 s t c h i p l a y o u t ( l a b o r a t L B L a n d F N A L ) 1 2? 2? CA , {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
{\colortbl ;\red0\green0\blue0;}
\viewkind4\uc1\pard\cf1\f0\fs16 This is the money spent on the chip layout and partial submission until Nov. 21st.\par
Right now we have only the italian contribution.\par
}
1 . 1 . 1 . 1 . 1 " 1 s t c h i p : l a y o u t l a b o r a t L B L ) 1 2? 2? `A `A CA `A rAA {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
\viewkind4\uc1\pard\f0\fs16 Cost:\par
this is all the cost of the chip up to the 1st submission\par
}
this is the remaining $ amount LBL needs to finish\par
the chip layout for the engineering run submission.\par
}
1 . 1 . 1 . 1 . 2 > 1 s t C h i p s u b m i s s i o n ( e n g . R u n ) 2 1 . 1 . 1 . 1 . 4 . 1 s t C h i p m a n u f a c t u r i n g 4 0 VA VA VA {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
{\colortbl ;\red0\green0\blue0;}
\viewkind4\uc1\pard\cf1\f0\fs16 Nov. 21 John Cooper said that this submission will be shared with BTev and\par
this is our share of the submission price.\par
}
4 @* 1 . 1 . 1 . 1 . 6 ( 1 s t C h i p e v a l u a t i o n 6 (A {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
\viewkind4\uc1\pard\f0\fs16 Most of the "low level" testing will be performed at LBL.\par
FNAL labor is mostly in testing the chip with the final DAQ chain at SiDet and Feynman.\par
}
1 . 1 . 1 . 1 . 9 6 1 s t C h i p r e a d y f o r h y b r i d s 9 {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
{\colortbl ;\red0\green0\blue0;}
\viewkind4\uc1\pard\cf1\f0\fs16 Schedule:\par
This is 1 month after receiving the Eng.run parts.\par
This is agressive and assumes the chip works without major problems.\par
}
ve parts available to put on hybrids\par
from this batch for hybrid evaluation, by end of March.\par
\par
\par
}
1 . 1 . 1 . 1 . 9 " 2 n d C h i p : l a y o u t l a y o u t 9 dA TA TA (A E {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
{\colortbl ;\red0\green0\blue0;}
\viewkind4\uc1\pard\cf1\f0\fs16 This starts after chip evaluation completes, but it could start earlier.\par
Labor:\par
moslty LBL labor.\par
We assume that FNAL will provide some help\par
\par
}
1 . 1 . 1 . 1 . 7 * 2 n d C h i p : s u b m i s s i o n 7 1 . 1 . 1 . 1 . 8 0 2 n d C h i p : m a n u f a c t u r i n g 8 gA cA cA {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
{\colortbl ;\red0\green0\blue0;}
\viewkind4\uc1\pard\cf1\f0\fs16 this is assumed to be an engineering run but could be\par
a mosis run which is cheaper\par
\par
}
1 . 1 . 1 . 1 . 9 , c o n t . C h i p e v a l u a t i o n 9 A {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
\viewkind4\uc1\pard\f0\fs16 Most of the "low level" testing will be performed at LBL.\par
FNAL labor is mostly in testing the chip with the final DAQ chain at SiDet and Feynman.\par
\par
}
1 . 1 . 1 . 1 . 1 8 6 2 n d C h i p r e a d y f o r h y b r i d s d s 1 8 1 . 1 . 1 . 1 . 1 9 . P r o d u c t i o n C h i p l a y o u t 1 9 YA IA IA A {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
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\viewkind4\uc1\pard\cf1\f0\fs16 Labor:\par
moslty LBL labor.\par
We assume that FNAL will provide some help\par
\par
\par
\cf0\par
}
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{\colortbl ;\red0\green0\blue0;}
\viewkind4\uc1\pard\cf1\f0\fs16 Milestone not linked to anything, it could start as early as 40\par
days after receiving the engineering run chips\par
}
il)\par
}
1 . 1 . 1 . 1 . 2 1 < P r o d u c t i o n c h i p m a n u f a c t u r i n g 2 1 ~A *uuA cA {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
{\colortbl ;\red0\green0\blue0;}
\viewkind4\uc1\pard\cf1\f0\fs16 We need about 5000 chips in the detector.\par
so we order 10,000 chips inculding yield.\par
This means we have to order 34 wafers (300 chips/wafer)\par
The minimum order is 10 wafers and costs 200,000 (this will be \par
split with D0).\par
The first 5 wafers cost $100,000, the rest cost 4000 each.\par
So the total is 100,000 + 116,000 = 216,000 \par
\par
}
1 . 1 . 1 . 1 . 1 4 < P r o d u c t i o n c h i p t e s t i n g s e t u p 1 4 A `A {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
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\viewkind4\uc1\pard\cf1\f0\fs16 Schedule:\par
This is time for getting programs setup and procedures worked\par
out for testing chips on wafers. \par
At the end of this this time we assume also that the 1st wafer is tested and ready for dicing.\par
Labor:\par
We assume that 1 scientist, 1 technician and 1 research associate will workfull time on this which is both for CDF and D0.\par
Below is the CDF share:\par
1. Scientist (50%)\par
2. Elect. Technician (50%)\par
3. postdoc (25%) support to CDF\par
4. Research Associate (50%)\par
5. Elect. Engineer (5%) chip designer expert \par
Cost:\par
William Wester estimated the cost (probe cards, equipment and material) for this task to be $7,500 plus $2,500 for contingency.\par
CDF share is :\par
$3,750 EQ\par
$1,250 CONT.\par
}
1 . 1 . 1 . 1 . 2 4 C D F c h i p s : T e s t & T e s t 2 4 0 Xs4A y {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
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\viewkind4\uc1\pard\cf1\f0\fs16 Schedule:\par
We are assuming 50 wafers, 300 chips/wafer, and testing rate of one wafer/day.\par
10 days added for sorting/dicing.\par
Labor:\par
1 scientist, 1 technician and 1 research associate will workfull time on this which is both for CDF and D0.\par
Below is the CDF share:\par
1. Scientist (50%)\par
2. Elect. Technician (50%)\par
3. postdoc (25%) support to CDF\par
4. Research Associate (50%)\par
5. Elect. Engineer (5%) chip designer expert \par
\par
}
4 @* P 1 . 1 . 1 . 1 . 2 6 6 P r o d u c t i o n C h i p s A v a i l a b l e 2 6 0 {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
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\viewkind4\uc1\pard\cf1\f0\fs16 This is the first wafer tested\par
}
1 . 1 . 1 . 1 . 2 7 , C h i p t e s t i n g C o m p l e t e 2 7 1 . 1 . 1 . 2 H y b r i d s 2 E6 2 MA x}5A ixqA {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
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\viewkind4\uc1\pard\cf1\f0\fs16 Runs (4 chips hybrids):\par
1. Prototype (milestone #1 "electrical stave test")\par
2. Contingency (milestone #2 "contingency electrical stave test")\par
3. Preproduction (milestone #3 "preproduction electrical stave test")\par
4. Production (milestone #4 "Production electrical stave test")\par
\cf0\par
\par
}
1 . 1 . 1 . 2 . 1 O u t e r l a y e r s 1 E6 2 6 A PA `A {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
{\colortbl ;\red0\green0\blue0;}
\viewkind4\uc1\pard\cf1\f0\fs16 Runs (4 chips hybrids):\par
1. Prototype (milestone #1 "electrical stave test")\par
2. Contingency (milestone #2 "contingency electrical stave test")\par
3. Preproduction (milestone #3 "preproduction electrical stave test")\par
4. Production (milestone #4 "Production electrical stave test")\par
\cf0\par
}
1 . 1 . 1 . 2 . 1 . 1 " H y b r i d # 1 L a y o u t 1 dcw? ? {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
\viewkind4\uc1\pard\f0\fs16 Cost of the layout (CAD etc.) is in the manufacturing cost.\par
}
4 ^ @* 1 . 1 . 1 . 2 . 1 . 3 0 H y b r i d # 1 m a n u f a c t u r i n g 3 JI]? JI]? eA `A `A [ {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
{\colortbl ;\red0\green0\blue0;}
\viewkind4\uc1\pard\cf1\f0\fs16 Schedule:\par
We are planning to order 40 hybrids (outer layers=4chips) to have enough for\par
building 5 staves plus spares. This will be all we get for stave prototyping until October 2002. \par
Cost:\par
is estimated at $64,000 including labor. \par
see file from Carl Hybrid-Stave-R+D-V3(1).\par
Associated parts are 20 bus cables (10 + 10 spares) and 20 MPC (10 plus 10 spares).\par
Added 30% cont. to the cost (64000)\par
\par
}
1 . 1 . 1 . 2 . 1 . 4 4 H y b r i d # 1 r e a d y f o r c h i p s 4 {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
\viewkind4\uc1\pard\f0\fs16 Schedule:\par
This is 10 days after receiving hybrids to allow for some minimal test.\par
}
un chips\par
}
1 . 1 . 1 . 2 . 1 . 5 ( H y b r i d # 1 a v a i l a b l e 5 {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
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\viewkind4\uc1\pard\cf1\f0\fs16 Available means chips are already mounted bonded and tested with the hybrids.\par
We are assuming this will be 3 weeks after substrate are available (test and load the substrate) and 2 weeks after chips are available (mount, bond and test).\par
This is part of our 1st project milestone (testing an electrical stave).\par
\par
}
1 . 1 . 1 . 2 . 1 . 6 * H y b r i d # 1 E v a l u a t i o n 6 w {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
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\viewkind4\uc1\pard\cf1\f0\fs16 Labor:\par
Test are done at LBL (no FNAL labor)\par
No labor cost for FNAL.\par
Total non FNAL Labor is estimated to be 2 full time physicists for prototype hybrid testing.\par
\par
}
estimate by pl\par
\par
}
1 . 1 . 1 . 2 . 1 . 8 $ H y b r i d # 2 L a y o u t 8 {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
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\viewkind4\uc1\pard\cf1\f0\fs16 We have time for possible relayout of hybrid as long as it happens in parallel with hybrid evaluation.\par
Hybrid #2 is meant to be used with 2nd round of engineering chips (Contingency Chips).\par
Labor:\par
\cf0 Cost of the layout (CAD etc.) is in the manufacturing cost.\par
\cf1\par
\par
}
4 t @* 1 . 1 . 1 . 2 . 1 . 8 0 H y b r i d # 2 m a n u f a c t u r i n g 8 eA D {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
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\viewkind4\uc1\pard\cf1\f0\fs16 General:\par
This is a contingency run in case the first hybrid run has major flaws, or modifications occured to the chip from first to second engineering run which requires hybrid modifications.\par
Cost:\par
see "Hybrid#1: manufacturing"\par
}
d of chips.\par
Cost:\par
see "Hybrid#1: manufacturing"\par
}
ch ramp up we will need 180 hybrids (12 weeks = 24 staves= 144 hybrids + spares)\par
Jan- April 32 staves\par
hybrids MPC Bus\par
144 24 48 needed\par
180 40 70 order including spares + yield\par
The cost is based on numbers needed and has no spares\par
as in the file hybrid-stave-R+D-V3(1)\par
\par
}
1 . 1 . 1 . 2 . 1 . 9 4 H y b r i d # 2 r e a d y f o r c h i p s 9 1 . 1 . 1 . 2 . 1 . 9 ( H y b r i d # 2 a v a i l a b l e 9 L {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
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\viewkind4\uc1\pard\cf1\f0\fs16 We are assuming this will be 3 weeks after substrate are available (test and load the substrate) and 2 weeks after chips are available (mount, bond and test).\par
\cf0\par
}
1 . 1 . 1 . 2 . 1 . 1 3 * H y b r i d # 2 E v a l u a t i o n 1 3 {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
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\viewkind4\uc1\pard\cf1\f0\fs16 Labor estimate by pl\par
\cf0\par
}
1 . 1 . 1 . 2 . 1 . 1 4 8 P r e p r o d u c t i o n h y b r i d L a y o u t 1 4 1 . 1 . 1 . 2 . 1 . 1 6 F P r e p r o d u c t i o n h y b r i d m a n u f a c t u r i n g 1 6 rA 5lA a {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
{\colortbl ;\red0\green0\blue0;}
\viewkind4\uc1\pard\cf1\f0\fs16 Schedule:\par
This has to cover stave production ramp up time.\par
Preproduction parts should be enough for building ~24 staves.\par
We assume to sustain a rate of 2 staves/week during preproduction (1 stave/day during production).\par
Cost:\par
Based on "cost for phase 2: preproduction phase" \par
V6.0 Mar-24-2002 (C.Haber, LBL)\par
Total cost is $151,802. Includes yield, labor, overhead, test cards and tests\par
\par
\par
}
L)\par
Total cost is $151,802. Includes yield, labor, overhead, test cards and tests\par
\par
\par
}
ar
}
o cost\par
\par
}
based on numbers needed and has no spares\par
as in the file hybrid-stave-R+D-V3(1)\par
added 30% cont. to cost\par
\par
}
1 . 1 . 1 . 2 . 1 . 1 3 2 S e t u p H y b r i d t e s t s t a n d 1 3 `6A .A {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
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\viewkind4\uc1\pard\cf1\f0\fs16 This is the test stand at LBL for updating the testing and burn-in capability there.\par
}
1 . 1 . 1 . 2 . 1 . 1 7 J P r e p r o d u c t i o n H y b r i d r e a d y f o r c h i p s 1 7 {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
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\viewkind4\uc1\pard\cf1\f0\fs16 This is 40 (manufacturing)+10 (testing and loading) days after submission as a possible first batch of the pre-production.\par
}
1 . 1 . 1 . 2 . 1 . 1 8 > P r e p r o d u c t i o n H y b r i d A v a i l a b l e 1 8 C {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
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\viewkind4\uc1\pard\cf1\f0\fs16 Schedule:\par
1 month after the production chips are available to be mounted on hybrids\par
2 weeks for mounting and testing the hybrid.\par
}
with chips.\par
}
1 . 1 . 1 . 2 . 1 . 1 9 < P r e p r o d u c t i o n H y b r i d c o m p l e t e 1 9
{\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
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\viewkind4\uc1\pard\cf1\f0\fs16 This assumes 10 hybrids delivered to Fermilab per week,\par
180 hybrids = 90 days of loading and testing\par
}
1 . 1 . 1 . 2 . 1 . 2 0 @ P r e p r o d u c t i o n H y b r i d E v a l u a t i o n 2 0 1 . 1 . 1 . 2 . 1 . 2 1 2 P r o d u c t i o n H y b r i d l a y o u t 2 1 {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
\viewkind4\uc1\pard\f0\fs16 This is optional.\par
Labor:\par
Cost of the layout (CAD etc.) is in the manufacturing cost.\par
\par
}
1 . 1 . 1 . 2 . 1 . 2 2 6 P r o d u c t i o n H y b r i d G o - a h e a d 2 2 ' {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
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\viewkind4\uc1\pard\cf1\f0\fs16 Schedule:\par
We need enough time to evaluate the preproduction (we put 40 days = 2 months).\par
Also we need some time to test the preproduction DAQ chain before committing to the production.\par
\par
}
lable for stave construction.\par
}
able for stave construction in\par
March. March produciton is covered by both preproduction hybrids and production hybrids.\par
\par
\par
}
1 . 1 . 1 . 2 . 1 . 2 3 B P r o d u c t i o n H y b r i d : m a n u f a c t u r i n g 2 3 A |
A N {\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}}
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\viewkind4\uc1\pard\cf1\f0\fs16 General:\par
Quantitiy needed is 1,080 + spares = 1200 hybrids.\par
\par
}
ar
split order 1/3 in FY 03 and 2/3 in FY 04\par
}
FY