The SVX3D Readout Chip

All components of the CDF II silicon system achieve their data readout through a set of 128-channel custom integrated circuit chips with the designation SVX3. The design of this chip is currently at revision D, and includes preamplification, a multi-cell analog storage pipeline, and simultaneous analog and digital operation capability. An optional data acquisition mode allows common-mode noise to be reduced independently for each chip by dynamic data-driven determination of pedestal levels.

The physical layout of the SVX3D die is shown in Figure 6. The chip has been manufactured in both rad-soft and 0.8-$\mu$m radiation hard CMOS processes, and in the latter version has been tested to operate successfully up to radiation doses of approximately 4 megarads[13].

Figure 6: A photo of the SVX3D readout chip is shown on the top. An organizational block diagram of its circuitry is given below. The analog and digital sections of the chip share a single die, with acceptably low crosstalk and noise.

Each channel of the SVX3D chip contains of a set of charge integrators followed by 47 cells of analog storage, and a Wilkenson analog-to-digital converter with 8 bits of precision, 7 of which are used. Readout in the back end of the digital section of the chip proceeds synchronously to a common bus and is controlled through serial instructions sent via multi-purpose mode and control lines. Sparsification, either with or without nearest-neighbor logic, is also provided and can be used whether or not the optional dynamic pedestal determination and subtraction mode is selected. The equivalent noise charge is roughly 500 electrons plus 21 electrons per picofarad at minimum bandwidth, rising to 750 e $+$ 53 e/pF at maximum bandwidth. Gain is selectable through an external resistor in the range between 300 and 4000 electrons per ADC count.

The chip is designed to operate at clock intervals between 100 and 400 ns, and takes approximately 1.2 $\mu$s to digitize 7 bits of readout data. Each chip dissipates approximately 500 mW of power and is 11.9 by 6.3 millimeters in dimension. The chips are mounted onto multi-layer thick film ceramic hybrids to form multi-chip modules that serve as the basic units of readout in the data acquisition system. Single sided hybrids made of 500 $\mu$m thick beryllia (BeO$_2$) are used for the SVX II. The ISL hybrids are made from aluminum nitride and have chips mounted on both sides of the substrates. Layer 00 hybrids are made of alumina (Al$_2$O$_3$) and are single-sided.

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