There are several requirements that dictate the design of the pigtail cable, as described in this section
 
 

1.1 Mechanical Requirements
 
 

The pigtail cable will leave the port card on the same side as the DOIMs. It must be sufficiently narrow to fit between the layer 3 and layer 4 DOIM transmitters, which is approximately 0.81 inches.

The cable must also avoid various obstacles along its run. It must allow the alignment probes access to alignment balls mounted near some of the bulkhead spokes. It also must avoid cooling pipes and the barrel position controllers. This will be accomplished by folding the cable to avoid the obstacles. A narrower cable will make this procedure less difficult.

Finally, the cable must be long enough to clear the ends of the barrel in z before connecting to the long Cu-Kapton cable, because of the limited space available above the barrels. From a mock-up of two barrels, we have determined that the length should be 24 inches to accommodate the longest cable run. In this case, the pigtail cables will connect to the long Cu-Kapton cables between 2 and 15 inches away from the end bulkhead.
 
 

1.2. Electrical Requirements
 
 

The pigtail cable carries power to supply the port card and the SVX3 chips. The power for the DOIMs and the digital section of the SVX3 chip is not regulated at the port card, so the resistance of the pigtail cable and the long Cu-Kapton cable will result in voltage swings as the current for these power lines changes. The trace widths of the power lines have been determined so as to give a voltage drop of less than 400 mV total across the long Cu-Kapton cable and the pigtail cable. To reduce the width of the pigtail, 250 mV of this voltage drop is allowed for the pigtail cable.

The connectors between the pigtail cable and the long Cu-Kapton cable have a maximum current rating of 1 Amp. For power lines near this limit, additional pins must be allocated to stay below the rating.

The impedance of the timing signals should match the characteristic impedance of the cable to which it will attach (3M 90101 series, 100 Ohms). The trace width and spacing were designed with this consideration. On an earlier prototype, the impedance was measured to be 104 Ohms, and the same design has been used for this specification.
 
 

1.3 Schedule
 
 

The pigtail prototypes should be available before the arrival of the revised port card. We estimate that a target date of late March will allow sufficient time to test the prototype and make any necessary revisions before the port card arrives. Furthermore, for testing purposes the pigtail should be able to connect directly to the junction board (which merges the discrete power and timing signal cables), bypassing the long Cu-Kapton cable. The connectors have been chosen to enable this, with the long Cu-Kapton cable acting as an "extension cord."
 
 

1.4 Design Considerations
 
 

Wherever possible, the design should be simplified in order to reduce the time required for layout. With this in mind, each trace has its own constant width along the entire length of the cable. We have also chosen to use Berg Electronics Conan connectors to connect between the pigtail and the long Cu-Kapton cable, since we have had good experience with the durability and reliability of these connectors.
 
 

The cable layout will be compatible with the pinout for the latest ceramic port card design, and the pin numbering as described in the following tables is consistent with that design. The far end of the cable should match the footprint of the Berg electronics Conan connector, part #91910-21141.

Figure 1 shows the trace width for each of the power lines so as to give the indicated maximum voltage drop between power and return lines. Also shown (labeled ``Current Margin") is the excess current-carrying capacity for the number of Conan connector pins that have been allocated. The power dissipated for each trace is also shown. For each supply line, the maximum current listed contains no less than 50% contingency over the actual maximum current measured on the SVX3 Rev. D chip.

Figure 2 shows the layout for the top side of the cable. Measured from the edge of the cable, the last two columns show where each trace begins and ends, in mils. Figure 3 shows the layout for the bottom side. Voltage return lines lie directly below the supply lines, and timing signals and their complements lie opposite one another. The total cable width is 0.606 inches. In cases where the trace widths differ slightly from the guidelines given in Figure 1, the widths given in Figures 2 and 3 take precedence.

Figure 4 shows the trace connections between the port card pins on one end and the Conan connector pins on the other end. There are a total of 9 spare pins, each of which should be connected to a solder pad. The first pin, labeled "Pigtail Shield" should also be connected to a solder pad accessible from both sides of the cable. The labels for the pins follow the convention used in the port card design layout. The digital timing signals and digital power lines are connected to one Conan connector, labeled P1, while the analog power lines and detector bias lines are connected to a second Conan connector, labeled P2.

In order to facilitate the connection/disconnection of the Conan connectors, the cable should be split at a length of 3 inches from the connectors. Each half should then be terminated with a multilayer board, in which the flex cable is sandwiched in two layers of G10. The Berg Conan connectors will be soldered directly onto the top rigid layer, which will allow sufficient force to be applied to mate and demate the connectors.
 
 

2.1 Additional Design Features
 
 

A couple of additional design constraints must be taken into account. The silicon detector bias supplies can have a potential difference of up to 200 V, thus care must be taken in routing their associated traces to avoid voltage breakdown. For traces with a soldermask, IPC guidelines dictate that adjacent traces on the same side of the Kapton must be separated by at least 15 mils. Figure 5 shows a routing configuration of the bias lines on the port card end that conforms to this guideline. The cable should be designed so that the traces at both ends of the cable have a soldermask in the region of the connector arrays.

On the Conan connector end of the pigtail, the separation of adjacent pins on the same row is not sufficient to ensure against breakdown. In order to minimize the number of skipped pins and provide an identical routing configuration for each layer, it is necessary to route one of the bias lines below the Kapton substrate, as shown in Figure 6.

A final design point is that the DOIM supply line +2VDOIM, along with the digital return line DGNDP, sinks current from the DOIM, which is powered by the +5VDOIM supply line. Thus the preferred configuration is for +2VDOIM and DGNDP traces to lie opposite the +5VDOIM trace. The location of these traces is indicated explicitly in Figures 2 and 3, and is illustrated in Figure 7.

The conceptual shape of the pigtail cable is shown in Figure 8.