FrontEnd Electronics and DAQ
Chapter 11 - Front-End Electronics and DAQ
The complete Chapter 11 document is available
here.
Figures
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Figure 11.1
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The run-II readout functional block diagram.
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Figure 11.2
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Plug-calorimeter readout.
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Figure 11.3
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Simplified schematic of the QIE ASIC.
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Figure 11.4
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Simplified schematic of the front-end module.
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Figure 11.5
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Noise performance of the prototype QIE5b4 ASIC compared with
the calorimeter resolution and the ideal curve for an 8-range, 8-bit
ADC system.
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Figure 11.6
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Schematic showing the general layout of the shower-max digitizer
boards.
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Figure 11.7
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Schematic showing the general layout of the shower-max VME
readout-boards.
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Figure 11.8
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Time dependence of the amplified central-strip-chamber wire signal as
observed. The top trace is $1 \mu$s per division, the bottom trace
200 ns per division.
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Figure 11.9
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Schematic showing the general operating principles of the
the INFN TDC chip.
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Figure 11.10
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Schematic showing the general layout of the hadron-TDC board.
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Figure 11.11
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Schematic diagram of JMC96 chip.
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Figure 11.12
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Block diagram of the 96 channel TDC boards.
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Figure 11.13
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A schematic of the CDF Data Acquisition system, showing
data flow from the front-end and trigger VME crates to the
Online Computing system.
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Figure 11.14
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Logical model of the Online Computing system.
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Figure 11.15
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A schematic of the Online Computing system. In the
actual implementation, the local-area network will be segmented
using routers and switches that are not shown.
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Figure 11.16
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A schematic of the CDF ALARMS system as configured for Run Ib
showing the consoles, Front End,
and control of the detector systems.