FrontEnd Electronics and DAQ

Chapter 11 - Front-End Electronics and DAQ

The complete Chapter 11 document is available here.

Figures

Figure 11.1 - The run-II readout functional block diagram.
Figure 11.2 - Plug-calorimeter readout.
Figure 11.3 - Simplified schematic of the QIE ASIC.
Figure 11.4 - Simplified schematic of the front-end module.
Figure 11.5 - Noise performance of the prototype QIE5b4 ASIC compared with the calorimeter resolution and the ideal curve for an 8-range, 8-bit ADC system.
Figure 11.6 - Schematic showing the general layout of the shower-max digitizer boards.
Figure 11.7 - Schematic showing the general layout of the shower-max VME readout-boards.
Figure 11.8 - Time dependence of the amplified central-strip-chamber wire signal as observed. The top trace is $1 \mu$s per division, the bottom trace 200 ns per division.
Figure 11.9 - Schematic showing the general operating principles of the the INFN TDC chip.
Figure 11.10 - Schematic showing the general layout of the hadron-TDC board.
Figure 11.11 - Schematic diagram of JMC96 chip.
Figure 11.12 - Block diagram of the 96 channel TDC boards.
Figure 11.13 - A schematic of the CDF Data Acquisition system, showing data flow from the front-end and trigger VME crates to the Online Computing system.
Figure 11.14 - Logical model of the Online Computing system.
Figure 11.15 - A schematic of the Online Computing system. In the actual implementation, the local-area network will be segmented using routers and switches that are not shown.
Figure 11.16 - A schematic of the CDF ALARMS system as configured for Run Ib showing the consoles, Front End, and control of the detector systems.